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| 1 rev. 1.1, may 05, 1999 MX10EXA xa 16-bit microcontroller family 64k flash/2k ram, watchdog, 2uarts preliminary feature ? 4.5v to 5.5v ? 64k bytes of on-chip flash program memory with in- system programming capability ? five flash blocks = two 8k byte blocks and three 16k byte blocks ? single supply voltage in-system programming of the flash memory, (vpp=vdd or vpp=12v ifdesired) ? boot rom contains low level flash programming routines for in-application programming and a default serial loader using the uart ? 2048 bytes of on-chip data ram ? supports off-chip program and data addressing up to 1 megabyte (20 address lines) ? three standard counter/timers with enhanced features all timers have a toggle output capability ? watchdog timer ? two enhanced uarts with independent baud rates ? seven software interrupts ? four 8-bit i/o ports, with 4 programmable output configurations for each pin ? 30 mhz operating frequency at 5v ? power saving operating modes: idle and power- down.wake-up from power-down via an external inter- rupt is supported. ? 44-pin plcc (MX10EXAqc) and 44-pin lqfp (MX10EXAuc) packages general description the MX10EXA is a member of philips 80c51 xa (extended architecture) family of high performance 16- bit single-chip microcontrollers. the MX10EXA contains 64k bytes of flash program memory, and provides three general purpose timers/ counters, a watchdog timer, dual uarts, and four gen- eral purpose i/o ports with programmable output con- figurations. pin configurations 44 plcc 44 lqfp a default serial loader program in the boot rom allows in-system programming (isp) of the flash memory with- out the need for a loader in the flash code. user pro- grams may erase and reprogram the flash memory at will through the use of standard routines contained in the boot rom (in-application programming). p/n:pm0625 MX10EXAqc p1.5/txd1 p1.6/t2 p1.7/t2ex rst p3.0/rxd0 nc p3.1/txd0 p3.2/int0 p3.3/int1 p3.4/t0 p3.5/t1/busw p0.4/a8d4 p0.5/a9d5 p0.6/a10d6 p0.7/a11d7 ea/vpp/wait nc ale psen p2.7/a19d15 p2.6/a18d14 p2.5/a17d13 p1.4/rxd1 p1.3/a3 p1.2/a2 p1.1/a1 p1.0/a0/wrh v ss v dd p0.0/a4d0 p0.1/a5d1 p0.2/a6d2 p0.3/a7d3 p3.6/wrl p3.7/rd xtal2 xtal1 v ss v dd p2.0/a12d8 p2.1/a13d9 p2.2/a14d10 p2.3/a15d11 p2.4/a16d12 64440 39 34 29 7 12 17 18 23 28 1 MX10EXAuc p1.5/txd1 p1.6/t2 p1.7/t2ex rst p3.0/rxd0 nc p3.1/txd0 p3.2/int0 p3.3/int1 p3.4/t0 p3.5/t1/busw p0.4/a8d4 p0.5/a9d5 p0.6/a10d6 p0.7/a11d7 ea/vpp/wait nc ale psen p2.7/a19d15 p2.6/a18d14 p2.5/a17d13 p1.4/rxd1 p1.3/a3 p1.2/a2 p1.1/a1 p1.0/a0/wrh v ss v dd p0.0/a4d0 p0.1/a5d1 p0.2/a6d2 p0.3/a7d3 p3.6/wrl p3.7/rd xtal2 xtal1 v ss v dd p2.0/a12d8 p2.1/a13d9 p2.2/a14d10 p2.3/a15d11 p2.4/a16d12 44 34 33 23 1 11 12 22
2 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA block diagram logic symbol xa cpu core 64k bytes flash program memory bus sfr bus data bus 2048 bytes static ram uart0 uart1 timer 0,1 timer 2 watchdog timer port 0 port 1 port 2 port 3 port 1 * not available on 40-pin dip package t2ex* t2* txd1 rxd1 a3 a2 a1 a0/wrh rxd0 txd0 int0 int1 t0 t1/busw wrl rd rst ea/wait psen ale address bus address and data bus port 2 port 0 port 3 alternate functions xtal2 xtal1 vdd vss 3 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA pin descriptions mnemonic pin. no. type name and function plcc lqfp v ss 1, 22 16,39 i ground: 0v reference. v dd 23, 44 17,38 i power supply: this is the power supply voltage for normal, idle, and power down operation. p0.0-p0.7 43-36 37-30 i/o port 0: port 0 is an 8-bit i/o port with a user-configurable output type. port 0 latches have 1s written to them and are configured in the quasi- bidirectional mode during reset. the operation of port 0 pins as inputs and outputs depends upon the port configuration selected. each port pin is configured independently. refer to the section on i/o port con- figuration and the dc electrical characteristics for details. when the external program/data bus is used, port 0 becomes the mul- tiplexed low data/instruction byte and address lines 4 through 11. p1.0-p1.7 2-9 40-44, i/o port 1: port 1 is an 8-bit i/o port with a user-configurable output type. 1-3 port 1 latches have 1s written to them and are configured in the quasi- bidirectional mode during reset. the operation of port 1 pins as inputs and outputs depends upon the port configuration selected. each port pin is configured independently. refer to the section on i/o port con- figuration and the dc electrical characteristics for details. port 1 also provides special functions as described below. 240o a0/wrh: address bit 0 of the external address bus when the external data bus is configured for an 8 bit width. when the external data bus is configured for a 16 bit width, this pin becomes the high byte write strobe. 341o a1: address bit 1 of the external address bus. 442o a2: address bit 2 of the external address bus. 543o a3: address bit 3 of the external address bus. 644i rxd1 (p1.4): receiver input for serial port 1. 71o txd1 (p1.5): transmitter output for serial port 1. 8 2 i/o t2 (p1.6): timer/counter 2 external count input/clockout. 93i t2ex (p1.7): timer/counter 2 reload/capture/direction control p2.0-p2.7 24-31 18-25 i/o port 2: port 2 is an 8-bit i/o port with a user-configurable output type. port 2 latches have 1s written to them and are configured in the quasi- bidirectional mode during reset. the operation of port 2 pins as inputs and outputs depends upon the port configuration selected. each port pin is configured independently. refer to the section on i/o port con- figuration and the dc electrical characteristics for details. when the external program/data bus is used in 16-bit mode, port 2 becomes the multiplexed high data/instruction byte and address lines 12 through 19. when the external program/data bus is used in 8-bit mode, the number of address lines that appear on port 2 is user pro- grammable. 4 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA mnemonic pin. no. type name and function plcc lqfp p3.0-p3.7 11,13-19 5,7-13 i/o port 3: port 3 is an 8-bit i/o port with a user configurable output type. port 3 latches have 1s written to them and are configured in the quasi- bidirectional mode during reset. the operation of port 3 pins as inputs and outputs depends upon the port configuration selected. each port pin is configured independently. refer to the section on i/o port con- figuration and the dc electrical characteristics for details. port 3 also provides various special functions as described below. 11 5 i rxd0 (p3.0): receiver input for serial port 0. 13 7 o txd0 (p3.1): transmitter output for serial port 0. 14 8 i int0 (p3.2): external interrupt 0 input. 15 9 i int1 (p3.3): external interrupt 1 input. 16 10 i/o t0 (p3.4): timer 0 external input, or timer 0 overflow output. 17 11 i/o t1/busw (p3.5): timer 1 external input, or timer 1 overflow output. the value on this pin is latched as the external reset input is released and defines the default external data bus width (busw). 0 = 8-bit bus and 1 = 16-bit bus. 18 12 o wrl (p3.6): external data memory low byte write strobe. 19 13 o rd (p3.7): external data memory read strobe. rst 10 4 i reset: a low on this pin resets the microcontroller, causing i/o ports and peripherals to take on their default states, and the processor to begin execution at the address contained in the reset vector. refer to the section on reset for details. ale 33 27 i/o address latch enable: a high output on the ale pin signals external circuitry to latch the address portion of the multiplexed address/data bus. a pulse on ale occurs only when it is needed in order to process a bus cycle. psen 32 26 o program store enable: the read strobe for external program memory. when the microcontroller accesses external program memory, psen is driven low in order to enable memory devices. psen is only active when external code accesses are performed. ea/wait 35 29 i external access/wait/programming supply voltage: the ea input /vpp determines whether the internal program memory of the microcontroller is used for code execution. the value on the ea pin is latched as the external reset input is released and applies during later execution. when latched as a 0, external program memory is used exclusively, when latched as a 1, internal program memory will be used up to its limit, and external program memory used above that point. after reset is released, this pin takes on the function of bus wait input. if wait is asserted high during any external bus access, that cycle will be extended until wait is released. during eprom programming, this pin is also the program- ming supply voltage input. xtal1 21 15 i crystal 1: input to the inverting amplifier used in the oscillator circuit and input to the internal clock generator circuits. xtal2 20 14 o crystal 2: output from the oscillator amplifier. 5 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA special function registers name description sfr bit functions and addresses reset address msb lsb value auxr auxiliary function register 44c enboot fmidle pwr_vld --- --- --- --- --- bcr bus configuration register 46a --- - - - - - - w aitd busd bc2 bc1 bc0 note 1 btrh bus timing register high byte 469 dw1 dw0 dwa1 dwa0 dr1 dr0 dra1 dra0 ff btrl bus timing register low byte 468 wm1 wm0 alew --- cr1 cr0 cra1 cra0 ef cs code segment 443 00 ds data segment 441 00 es extra segment 442 00 33f 33e 33d 33c 33b 33a 339 338 ieh* interrupt enable high byte 427 --- --- --- --- eti1 eri1 eti0 eri0 00 337 336 335 334 333 332 331 330 iel* interrupt enable low byte 426 ea --- --- et2 et1 ex1 et0 ex0 00 ipa0 interrupt priority 0 4a0 --- pt0 --- px0 00 ipa1 interrupt priority 1 4a1 --- pt1 --- px1 00 ipa2 interrupt priority 2 4a2 --- --- --- pt2 00 ipa4 interrupt priority 4 4a4 --- pti0 --- pri0 00 ipa5 interrupt priority 5 4a5 --- pti1 --- pri1 00 387 386 385 384 383 382 381 380 p0* port 0 430 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 ff 38f 38e 38d 38c 38b 38a 389 388 p1* port 1 431 t2ex t2 txd1 rxd1 a3 a2 a1 wrh ff 397 396 395 394 393 392 391 390 p2* port 2 432 p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 ff 39f 39e 39d 39c 39b 39a 399 398 p3* port 3 433 rd wr t1 t0 int1 int0 txd0 rxd0 ff p0cfga port 0 configuration a 470 note 5 p1cfga port 1 configuration a 471 note 5 p2cfga port 2 configuration a 472 note 5 p3cfga port 3 configuration a 473 note 5 p0cfgb port 0 configuration b 4f0 note 5 p1cfgb port 1 configuration b 4f1 note 5 p2cfgb port 2 configuration b 4f2 note 5 p3cfgb port 3 configuration b 4f3 note 5 6 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA name description sfr bit functions and addresses reset address msb lsb value 227 226 225 224 223 222 221 220 pcon* power control register 404 --- --- --- --- --- --- pd idl 00 20f 20e 20d 20c 20b 20a 209 208 pswh* program status word 401 sm tm rs1 rs0 im3 im2 im1 i m0 note 2 (high byte) 207 206 205 204 203 202 201 200 pswl* program status word 400 c ac --- --- --- v n z note 2 (low byte) 217 216 215 214 213 212 211 210 psw51* 80c51 compatible psw 402 c ac f0 rs1 rs0 v f1 p note 3 rth0 timer 0 extended reload, 455 00 high byte rth1 timer 1 extended reload, 457 00 high byte rtl0 timer 0 extended reload, 454 00 low byte rtl1 timer 1 extended reload, 456 00 low byte 307 306 305 304 303 302 301 300 s0con* serial port 0 control register 420 sm0_0 sm1_0 sm2_0 ren_0 tb8_0 rb8_0 ti_0 ri_0 00 30f 30e 30d 30c 30b 30a 309 308 s0stat* serial port 0 extended status 421 --- --- --- --- fe0 br0 oe0 stint0 00 s0buf serial port 0 buffer register 460 x s0addr serial port 0 address register 461 0 s0aden serial port 0 address enable 462 00 register 327 326 325 324 323 322 321 320 s1con* serial port 1 control register 424 sm0_1 sm1_1 sm2_1 ren_1 tb8_1 rb8_1 ti_1 ri_1 00 32f 32e 32d 32c 32b 32a 329 328 s1stat* serial port 1 extended status 425 --- --- --- --- fe1 br1 oe1 stint1 00 s1buf serial port 1 buffer register 464 x s1addr serial port 1 address register 465 00 s1aden serial port 1 address enabler 466 00 register 7 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA name description sfr bit functions and addresses reset address msb lsb value scr system configuration register 440 --- --- --- --- pt1 pt0 cm pz 00 21f 21e 21d 21c 21b 21a 219 218 ssel* segment selection register 403 eswen r6seg r5seg r4seg r3seg r2seg r1seg r0seg 00 swe software interrupt enable 47a --- swe7 swe6 swe5 swe4 swe3 swe2 swe1 00 357 356 355 354 353 352 351 350 swr* software interrupt request 42a --- swr7 swr6 swr5 swr4 swr3 swr2 swr1 00 2c7 2c6 2c5 2c4 2c3 2c2 2c1 2c0 t2con* timer 2 control register 418 tf2 exf2 rclk0 tclk0 exen2 tr2 c/t2 cp/rl2 00 2cf 2ce 2cd 2cc 2cb 2ca 2c9 2c8 t2mod* timer 2 mode control 419 --- --- rclk1 tclk1 --- --- t2oe dcen 00 th2 timer 2 high byte 459 00 tl2 timer 2 low byte 458 00 t2caph timer 2 capture register, 45b 00 high byte t2capl timer 2 capture register, 45a 00 low byte 287 286 285 284 283 282 281 280 tcon* timer 0 and 1 control register 410 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00 th0 timer 0 high byte 451 00 th1 timer 1 high byte 453 00 tl0 timer 0 low byte 450 00 tl1 timer 1 low byte 452 00 tmod timer 0 and 1 mode control 45c gate c/t m1 m0 gate c/t m1 m0 00 28f 28e 28d 28c 28b 28a 289 288 tstat* timer 0 and 1 extended status 411 --- --- --- --- --- t1oe --- t0oe 00 2ff 2fe 2fd 2fc 2fb 2fa 2f9 2f8 wdcon* watchdog control register 41f pre2 pre1 pre0 --- --- wdrun wdtof --- note 6 wdl watchdog timer reload 45f 00 wfeed1 watchdog feed 1 45d x wfeed2 watchdog feed 2 45e x 8 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA notes: * sfrs are bit addressable. 1. at reset, the bcr register is loaded with the binary value 0000 0a11, where "a" is the value on the busw pin. this defaults the address bus size to 20 bits, since the MX10EXA has only 20 address lines. 2. sfr is loaded from the reset vector. 3. all bits except f1, f0, and p are loaded from the reset vector. those bits are all 0. 4. unimplemented bits in sfrs are x (unknown) at all times. ones should not be written to these bits since they may be used for other purposes in future xa derivatives. the reset value shown for these bits is 0. 5. port configurations default to quasi-bidirectional when the xa begins execution from internal code memory after reset, based on the condition found on the ea pin. thus all pncfga registers will contain ff and pncfgb registers will contain 00. when the xa begins execution using external code memory, the default configuration for pins that are associated with the external bus will be push-pull. the pncfga and pncfgb register contents will reflect this difference. 6. the wdcon reset value is e6 for a watchdog reset, e4 for all other reset causes. 7. the MX10EXA implements an 8-bit sfr bus. all sfr accesses must be 8-bit operations. attempts to write 16 bits to an sfr will actually write only the lower 8 bits. sixteen bit sfr reads will return undefined data in the upper byte. 9 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA fffffh data segment 0 0800h 07ffh 0400h 03ffh 0040h 003fh 0020h 001fh 0000h data memory (indirectly addressed, off-chip) data memory (indirectly addressed, on chip) data memory (directly and indirectly addressable, on chip) bit-addressable data area 2k bytes on-chip data memory (ram) data memory (directly and indirectly addressable, on chip) figure 1. xa data memory map fffffh other data segments 0400h 03ffh 0040h 003fh 0020h 001fh 0000h data memory (indirectly addressed, off-chip) data memory (directly and indirectly addressable, off-chip) bit-addressable data area directly addressed data (1k per segment) data memory (directly and indirectly addressable, off-chip) figure 1. xa program memory map fffffh 10000h ffffh ffffh f800h 2k byte boot rom 0000h note:the boot rom replaces the top 2k bytes of flash memory when it is enable via the xxx bit in xxx. up to 1m bytes total code memory 64k bytes on-chip code memory 10 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA flash eprom memory general description the xa flash memory augments eprom functionality with in-circuit electrical erasure and programming. the flash can be read and written as bytes. the chip erase operation will erase the entire program memory. the block erase function can erase any single flash block. in-cir- cuit programming and standard parallel programming are both available. on-chip erase and write timing genera- tion contribute to a user friendly programming interface. the xa flash reliably stores memory contents even af- ter 10,000 erase and program cycles. the cell is designed to optimize the erase and programming mechanisms. in addition, the combination of advanced tunnel oxide pro- cessing and low internal electric fields for erase and pro- gramming operations produces reliable cycling. for in- system programming, the xa can use a single +5 v power supply. faster in-system programming may be obtained, if required, through the use of a+12v vpp sup- ply. parallel programming (using separate programming hardware) uses a+12v vpp supply. features ? flash eprom internal program memory with block erase. ? internal 2k byte fixed boot rom, containing low-level programming routines and a default loader. the boot rom can be turned off to provide access to the full 64k byte flash memory. ? boot vector allows user provided flash loader code to reside anywhere in the flash memory space. this configuration provides flexibility to the user. ? default loader in boot rom allows programming via the serial port without the need for a user provided loader. ? up to 1mbyte external program memory if the internal program memory is disabled(ea=0). ? programming and erase voltage vpp = vdd or 12v 5% for isp, 12v 5% for parallel programming. ? read/programming/erase: - byte-wise read (60 ns access time at 4.5 v). - byte programming (40us). - typical erase times : block erase (8k bytes or 16k bytes) in 1.6 seconds. full erase (64k bytes) in 1.6 seconds. ? in-circuit programming via user selected method, typi- cally rs232 or parallel i/o port interface. ? programmable security for the code in the flash ? 10,000 minimum erase/program cycles ? 10 year minimum data retention. 11 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA capabilities of the philips 89c51 flash- based microcontrollers flash organization the xa contains 64k bytes of flash program memory. this memory is organized as 5 separate blocks. the first two blocks are 8k bytes in size, filling the program memory space from address 0 through 3fff hex. the final three blocks are 16k bytes in size and occupy ad- dresses from 4000 through ffff hex. figure 3 depicts the flash memory configuration. flash programming and erasure the xa flash microcontroller supports a number of pro- gramming possibilities for the on-chip flash memory. the flash memory may be programmed in a parallel fashion on standard programming equipment in a manner similar to an eprom microcontroller. the xa microcontroller is able to program its own flash memory while the applica- tion code is running. also, a default loader built into a boot rom allows programming blank devices serially through the uart. using any of these types of programming, any of the individual blocks may be erased separately, or the entire chip may be erased. programming of the flash memory is accomplished one byte at a t ime. boot rom when the microcontroller programs its own flash memory, all of the low level details are handled by code that is permanently contained in a 2k byte boot rom that is separate from the flash memory. a user program simply calls the entry point with the appropriate parameters to accomplish the desired operation. boot rom operations include things like: erase block, program byte, verity byte, program security lock bit, etc. the boot rom overlays the program memory space at the top of the address space from f800 to ffff hex, when it is enabled by setting the enboot bit at auxr1.7.. the boot rom may be turned off so that the upper 2k bytes of flash program memory are accessible for execution. enboot and pwr_vld setting the enboot bit in the auxr register enables the boot rom and activates the on-chip v pp generator if v pp is connected to rather than 12v externally. the pwr_vld flag indicates that v pp is available for programming and erase operations. this flag should be checked prior to calling the boot rom for programming and erase services. when enboot is set, it typically takes 5 microseconds for the internal programming voltage to be ready. the enboot bit will automatically be set if the status byte is non-zero during reset, or when psen is low, ale is high, and ea is high at the falling edge of reset. other- wise, enboot will be cleared during reset. when programming functions are not needed, enboot may be cleared. this enables access to the 2k bytes of flash code memory that is overlaid by the boot rom, allowing a full 64k bytes of flash cede memory. figure 3. flash memory configuration ffff ffff c000 8000 f800 4000 2000 0000 block 4 16k bytes boot rom block 3 16k bytes block 2 16k bytes program address block 1 8k bytes block 0 8k bytes 12 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA fmidle the fmidle bit in the auxr register allows saving addi- tional power by turning off the flash memory when the cpu is in the idle mode. this must be done just prior to initiating the idle mode, as shown below. or auxr, #$40 ;set flash memory to idle mode. or pcon, #$0l ;turn on idle mode. . . ;execution resumes here when idle mode terminates. when the flash memory is put into the idle mode by setting fmidle, restarting the cpu upon exiting idle mode takes slightly longer, about 3 microseconds. how- ever, the standby current consumed by the flash memory is reduced from about 8ma to about 1ma. default loader a default loader that accepts programming commands in a predetermined format is contained permanently in the boot rom. a factory fresh device will enter this loader automatically if it is powered up without first being pro- grammed by the user. loader commands include func- tions such as erase block; program flash memory; read flash memory; and blank check. boot vector the xa contains two special flash registers: the boot vector and the status byte. the "boot vector" allows forcing the execution of a user supplied flash loader upon reset, under two specific sets of conditions. at the falling edge of reset, the xa exam- ines the contents of the status byte. if the status byte is set to zero, power-up execution starts at location 0000h, which is the normal start address of the users application code. when the status byte is set to a value other than zero, the boot vector is used as the reset vector (4 bytes), including the boot program counter (bpc) and the boot psw (bpsw). the factory default settings are 8000h for the bpsw and f800h for the bpc, which corresponds to the address f900h for the factory masked-rom isp boot loader. the status byte is automatically set to a non-zero value when a programming error occurs. a cus- tom boot loader can be written with the boot vector set to the custom boot loader. note: when erasing the status byte or boot vector, these bytes are erased at the same time. it is necessary to reprogram the boot vector after erasing and updating the status byte. hardware activation of the boot vector program execution at the boot vector may also be forced from outside of the microcontroller by setting the correct state on a few pins. while reset is asserted, the psen pin must be pulled low, the ale pin allowed to float high (need not be pulled up externally), and the ea pin driven to a logic high (or up to v pp ). then reset may be released. this is the same effect as having a non-zero status byte. this allows building an application that will normally ex- ecute the end users code but can be manually forced into isp operation. the boot rom is enabled when use of the boot vector is forced as described above, so the branch may go to the default loader. conversely, user code in the top 2k bytes of the flash memory may not be executed when the boot vector is used. if the factory defauolt setting for the bpc (f800h) is changed, it will no longer point to the isp masked-rom boot loader code. if this happens, the only possible way to change the contents of the boot vector is through the parallel programming method, provided that the end user application does not contain a customized loader that provides for erasing and reprogramming of the boot vec- tor and status byte. after programming the flash, the status byte should be erased to zero in order to allow ex ecution of the users application code beginning at address 0000h. 13 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA in-system programming (isp) in-system programming (isp) is performed without re- moving the microcontroller from the system. the in-sys- tem programming (isp) facility consists of a series of internal hardware resources coupled with internal firm- ware to facilitate remote programming of the xa through the serial port. the in-system programming (isp) facility has made in- circuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area. the isp function uses five pins: txd, rxd, v ss , and v pp (see figure 4). only a small connector needs to be avail- able to interface your application to an external circuit in order to use this feature. the v pp supply should be ad- equately decoupled and v pp not allowed to exceed data sheet limits. using in-system programming (isp) when isp mode is entered, the default loader first dis- ables the watchdog timer to prevent a watchdog reset from occurring during programming. the isp feature allows for a wide range of baud rates to be used in the application, independent of the oscillator frequency. it is also adaptable to a wide range of oscilla- tor frequencies. this is accomplished by measuring the bit-time of a single bit in a received character. this infor- mation is then used to program the baud rate in terms of timer counts based on the oscillator frequency. the isp feature requires that an initial character (a lowercase f) be sent to the xa to establish the baud rate. the isp firmware provides auto-echo of received characters. once baud rate initialization has been performed, the isp firmware will only accept specific intel hex-type records. intel hex records consist of ascii characters used to represent hexadecimal values and are summa- rized below: :nnaaaarrdd..ddcc 14 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA isp facility. the maximum number of data bytes in a record is limited to 16 (decimal). isp commands are sum- marized in table 1. as a record is received by the xa, the information in the record is stored internally and a checksum calculation is performed. the operation indicated by the record type is not performed until the entire record has been received. should an error occur in the checksum, the xa will send an "x" out the serial port indicating a checksum error. if the checksum calculation is found to match the checksum in the record, then the command will be ex- ecuted. in most cases, successful reception of the record will be indicated by transmitting a "." character out the serial port (displaying the contents of the internal pro- gram memory is an exception). in the case of a data record (record type 00), an addi- tional check is made. a "." character will not be sent unless the record checksum matched the calculated checksum and all of the bytes in the record were suc- cessfully programmed. for a data record, an "x" indi- cates that the checksum failed to match, and an "r" character indicates that one of the bytes did not prop- erty program. the isp facility was designed so that specific crystal frequencies were not required in order to generate baud rates or time the programming pulses. user supplied loader a user program can simply decide at any time, for any reason, to begin flash programming operations. all it has to do in advance is to instruct external circuitry to apply +5v or +12v to the v pp pin, and make certain that the boot rom is enabled. user code may contain a loader designed to replace the application code contained in the flash memory by loading new code through any com- munication medium available in the application. this is completely flexible and defined by the designer of the system. it could be done serially using rs-232, serially using some other method, or even parallel over a user defined i/o port. the user has the freedom to choose a method that does not interfere with the application cir- cuit. as an added feature, the application program may also use the flash memory as a long term data storage, saving configuration information, sensor readings, or any other desired data. the actual loader code would typically be programmed by the user into the microcontroller in a parallel fashion or via the default loader during their manufacturing pro- cess. the entire initial flash contents may be programmed at that time, or the rest of the application may be pro- grammed into the flash memory at a later time, possibly using the loader code to do the programming. this application controlled programming capability allows for the possibility of changing the application code in the field. if the application circuit is embedded in a pc, or has a way to establish a telephone data link to a users or manufacturers computer, new code could be down- loaded from diskette or a manuf acturers support sys- tem. there is even the possibility of conducting very specialized remote testing of a failing circuit board by the manufacturer by remotely programming a series of detailed test programs into the application board and checking the results. any user supplied loader should take the watchdog timer into account. typically, the watchdog timer would be dis- abled upon entry to the loader if it might be running, in order to prevent a watchdog reset from occurring during programming. 15 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA table 1. intel-hex records used by in-system programming record type commandidata function 00 or 80 data record :nnaaaa00dd....ddcc where: nn = number of bytes (hex) in record aaaa = memory address of first byte in record dd....dd= data bytes cc = checksum example:10008000af5f67f0602703e0322cfa92007780c3fd 0l or 81 end of file (eof), no operation :xxxxxx0lcc where: xxxxxx = required field, but value is a "don't care cc = checksum example:00000001ff 83 miscellaneous write functions :nnxxxx83 ffssddcc where: nn = number of bytes (hex) in record xxxx = required field, but value is a "don't care 83 = write function ff = subfunction code ss = selection code dd = data input (as needed) cc = checksum subfunction code = 0l (erase blocks) ff = 0l ss = block number in bits 7:5, bits 4:0 = zeros block 0 : = 00h block 1 : ss = 20h block 2 : ss = 40h block 3 : ss = 80h block 4 : ss = c0h example:0200008301203c erase block 1 subfunction code =04 (erase boot vector and status byte) ff = 04 as = don't care dd = don't care example:010000830478 erase boot vector and status byte subtunction code = 05 (program security bits) ff = 05 ss = 00 program security bit 1 (inhibit writing to flash) 01 program security bit 2 (inhibit flash verify) 02 program security bit 3 (disable external memory) example:02000083050175 program security bit 2 subtunction code = 06 (program status byte or boot vector) ff = 06 ss = 00 program status byte 0l program boot vector example:020000830601fc78 program boot vector to fc00h 16 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA record type commandidata function 84 display device data or blank check - record type 84 causes the contents of the entire flash array to be sent out the serial port in a formatted display. this display consists of an address and the contents of 16 bytes starting with that address. no display of the device contents will occur it security bit 2 has been programmed. the dumping of the device data to the serial port is terminated by the reception of any character. general format of function 84 :05xxxx84sssseeeeffcc where: 05 = number of bytes (hex) in record xxxx = required field, but value is a "don't care 84 = "display device data or blank check" function code ssss = starting address eeee = ending address ff = subfunction 00 = display data 01 = blank check cc = checksum example:0500008440004fff00e9 display 4000-4fff 85 miscellaneous read functions general format of function 85 :02xxxx85ffsscc where: 02 = number of bytes (hex) in record xxxx = required field, but value is a "don't care 85 = "miscellaneous read" function code ffss = subfunction and selection code 0000 = read signature byte - manufacturer id(15h) 0001 = read signature byte - device id # 1(eah) 0002 = read signature byte - device id # 2(xa= 54h)) 0700 = read security bits (returned value bits 3:1 = sb3,sb2,sbl) 0701 = read status byte 0702 = read boot vector cc = checksum example:02000085000178 read signature byte - device id # 1 17 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA in-application programming method several application program interface (api) calls are available for use by an application program to permit selective erasing and programming of flash sectors. all calls are made through a common interface, pgm_mtp. the pro- gramming functions are selected by setting up the microcontroller's registers before making a call to pgm_mtp at fffoh. results are returned in the registers. the api calls are shown in table 2. table 2. api calls api call p arameter program data byte input parameters: r0h = 02h or 92h r6 = address of byte to program r4l = byte to program return parameter r4l = 00 if pass, non-zero if fail erase block input parameters: r0h = 01h or 93h r6h = block number in bits 7:5, bits 4:0 = "0" block 0 : r6h = 00h block 1 : r6h = 20h block 2 : r6h = 40h block 3 : r6h = 80h block 4 : r6h = c0h rel = 00h return parameter r4l = 00 if pass, non-zero if fail erase bpc and input parameters: status byte roh =04h return parameter r4l =00 if pass, non-zero if fail program security input parameters: bit r0h = 05h r6h = 00h r6l = 00h - security bit # 1 (inhibit writing to flash) 0lh - security bit # 2 (inhibit flash verify) 02h - security bit # 3 (disable external memory) return parameter:none program status input parameters: byte r0h = 60h r6h = 00h r6l = 00h- program status byte r4l = status byte return parameter r4l = 00 if pass, non-zero if fail program bpc high input parameters: byte r0h = 06h r6h = 00h r6l = 0lh - program bpc r4l = bpc[15:8] (bpc[7:0] unchanged) return parameter r4l = 00 if pass, non-zero if fail 18 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA api call p arameter read device data input parameters: r0h = 03h r6 = address of byte to read return parameter r4l = value of byte read read manufacturer input parameters: id r0h = 00h r6h = 00h r6l = 00h (manufacturer id) return parameter r4l = value of byte read read device id # 1 input parameters: r0h = 00h r6h = 00h r6l = 0lh (device id # 1) return parameter r4l =value of byte read read device id # 2 input parameters: r0h = 00h r6h =00h r6l = 02h (device id # 2) return parameter r4l = value of byte read read security bits input parameters: r0h = 07h r6h = 00h r6l = 00h (security bits) return parameter r4l = value of byte read r4l[3:l] = sb3, sb2, sb1 read status byte input parameters: r0h = 07h r6h = 00h r6l = 0lh (status byte) return parameter r4l = value of bpc[l5:8] read bpc input parameters: r0h = 07h r6h = 00h r6l = 02h (boot vector) return parameter r4l = value of byte read 19 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA api call p arameter program all zero input parameters: r0h = 90h r6h = block number in bits 7:5, bits 4:0 = '0' block 0 : r6h = 00h block 1 : r6h = 20h block 2 : r6h = 40h block 3 : r6h = 80h block 4 : r6h = c0h r6l = 00h return parameters: r4l = 00 if pass, non-zero if fail erase chip input parameters: r0h = 91h r4l = 55h (after chip erase, return to caller) = aah (after chip erase, reset chip) = others: error return parameters: r4l = 00 if pass, non-zero if fail program special input parameters: cell r0h = 94h r6 = special cell address 0000h: program bpsw[7:0] 000lh: program bpsw[15:8] 0002h: program bpc[7:0] 0003h: program bpc[15:8] 0004b: program status byte 000ah:program security bit #1 000ch:program security bit #2 000eh:program security bit #3 r4l =byte value to program return parameters: r4l =00 if pass, non-zero if fail erase special cell input parameters: r0h = 95h r6 = special cell address 0000h: erase dpsw[7:0] 000lh: erase dpsw[15:8] 0002h: erase bpc(7:0) 0003h: erase bpc[15:8] 0004h: erase status byte return parameters: r4l = 00 if pass, non-zero if fail 20 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA api call p arameter read special cell input parameters: r0h = 96h r6 = special cell address 0000h: read bpsw[7:0] 000lh: read bpsw[15:8] 0002h: read bpc[7:0] 0003h: read bpc[15:8] 0004h: read status byte 0006h: read manufacturer id 0007h: read device id #1 0008h: read device id #2 000ah: read security bit #1 000ch: read security bit #2 000eh: read security bit #3 return parameters: r4l = value of byte read security the security feature protects against software piracy and prevents the contents of the flash from being read. the security lock bits are located in flash. the xa has 3 programmable security lock bits that will provide different levels of protection for the on-chip code and data (see table 3). table 3. security lock bits 1 protection description level sb1 sb2 sb3 1 0 0 0 no program security features enabled 2 1 0 0 inhibit writing to flash. also, movc instructions executed from external program memory are disabled from fetching code bytes from internal memory. 3 1 1 0 same as level 2, plus program verification is disabled 4 1 1 1 same as level 3, plus external execution is disabled. note: 1. any other combination of the lock bits is not defined. 21 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA xa timer/counters the xa has two standard 16-bit enhanced timer/counters: timer 0 and timer 1.additionally, it has a third 16-bit up/ down timer/counter, t2. a central timing generator in the xa core provides the time-base for all xa timers and counters. the timer/event counters can perform the fol- lowing functions: - measure time intervals and pulse duration - count external events - generate interrupt requests - generate pwm or timed output waveforms all of the timer/counters (timer 0, timer 1 and timer 2) can be independently programmed to operate either as timers or event counters via the c/t bit in the tncon register. all timers count up unless otherwise stated. these timers may be dynamically read during program execution. the base clock rate of all of the timers is user program- mable. this applies to timers t0, t1, and t2 when run- ning in timer mode (as opposed to counter mode), and the watchdog timer. the clock driving the timers is called tclk and is determined by the setting of two bits (pt1, pt0) in the system configuration register (scr). the frequency of tclk may be selected to be the oscillator input divided by 4 (osc/4), the oscillator input divided by 16 (osc/16), or the oscillator input divided by 64 (osc/ 64). this gives a range of possibilities for the xa timer functions, including baud rate generation, timer 2 cap- ture. note that this single rate setting applies to all of the timers. when timers t0, t1, or t2 are used in the counter mode, the register will increment whenever a falling edge (high to low transition) is detected on the external input pin corresponding to the timer clock. these inputs are sampled once every 2 oscillator cycles, so it can take as many as 4 oscillator cycles to detect a transition. thus the maximum count rate that can be supported is osc/4. the duty cycle of the timer clock inputs is not important, but any high or low state on the timer clock input pins must be present for 2 oscillator cycles before it is guaranteed to be seen by the timer logic. timer 0 and timer 1 the timer or counter function is selected by control bits c/t in the special function register tmod. these two timer/counters have four operating modes, which are selected by bit-pairs (ml, m0) in the tmod register. timer modes 1, 2, and 3 in xa are kept identical to the 80c51 timer modes for code compatibility. only the mode 0 is replaced in the xa by a more powerful 16-bit auto- reload mode. this will give the xa timers a much larger range when used as time bases. the recommended ml, m0 settings for the different modes are shown in figure 6. 22 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA pt1 pt0 operating prescaler selection. 0 0 osc/4 0 1 osc/16 1 0 osc/64 1 1 reserved cm compatibility mode allows the xa to execute most translated 80c51 code on the xa. the xa register file must copy the 80c51 mapping to data memory and mimic the 80c51 indirect addressing scheme. pz page zero mode forces all program and data addresses to 16-bits only. this saves stack space and speeds up execution but limits memory access to 64k. figure 5. system configuration register (scr) gate gating control when set. timer/counter "n" is enabled only while "intn" pin is high and "trn" control bit is set. when cleared timer "n" is enabled whenever "trn" control bit is set. c/t timer or counter selector cleared for timer operation (input from internal system clock.) set for counter operation (input from "tn" input pin). m1 m0 operating 0 0 16-bit auto-reload timer/counter 0 1 16-bit non-auto-reload timer/counter 1 0 8-bit auto-reload timer/counter 1 1 dual 8-bit timer mode (timer 0 only) figure 6. timer/counter mode control (tmod) register - - - pt1 msb lsb pt0 cm pz not bit addressable reset value:00h - scr address:440 gate c/t timer 1 timer 0 m1 m0 gate msb lsb c/t m1 m0 not bit addressable reset value:00h address:45c tmod 23 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA new enhanced mode 0 for timers t0 or t1 the 13-bit count mode on the 80c51 (current mode 0) has been replaced in the xa with a 16- bit auto-reload mode. four additional 8-bit data registers (two per timer: rthn and rtln) are created to hold the auto-reload values. in this mode, the th overflow will set the tf flag in the tcon register and cause both the tl and th counters to be loaded from the rtl and rth registers respectively. these new sfrs will also be used to hold the tl reload data in the 8-bit auto-reload mode (mode 2) instead of th. the overflow rate for timer 0 or timer 1 in mode 0 may be calculated as follows: timer_rate = osc/(n*(65536 - timer_reload_value)) where n = the tclk prescaler value: 4 (default), 16, or 64. mode 1 mode 1 is the 16-bit non-auto reload mode. mode 2 mode 2 configures the timer register as an 8-bit counter (tln) with automatic reload. overflow from tln not only sets tfn, but also reloads tln with the contents of rtln, which is preset by software. the reload leaves thn un- changed. mode 2 operation is the same for timer/counter 0. the overflow rate for timer 0 or timer 1 in mode 2 may be calculated as follows: timer_rate = osc/(n * (256 - timer_reload_value)) where n = the tclk prescaler value: 4, 16, or 64. mode 3 timer 1 in mode 3 simply holds its count. the effect is the same as setting tr1 =0. timer 0 in mode 3 establishes tl0 and th0 as two sepa- rate counters. tl0 uses the timer 0 control bits: cit; gate, tr0, int0, and tf0. th0 is locked into a timer function and takes over the use of tr1 and tf1 from timer 1. thus, th0 now controls the "timer 1" interrupt. mode 3 is provided for applications requiring an extra 8- bit timer. when timer 0 is in mode 3, timer 1 can be turned on and off by switching it out of and into its own mode 3, or can still be used by the serial port as a baud rate generator, or in fact, in any application not requiring an interrupt. tf1 tr1 tf0 tr0 ie1 msb lsb it1 ie0 it0 bit addressable reset value:00h address:410 tcon bit symbol function tcon.7 tf1 timer 1 overflow flag. set by hardware on timer/counter overflow. this flag will not be set if t1oe(tstat.2) is set. cleared by hardware when processor vectors to interrupt routine, or by clearing the bit in software. tcon.6 tr1 timer 1 run control bit. set/cleared by software to turn timer/counter 1 on/off. tcon.5 tf0 timer 0 overflow flag. set by hardware on timer/counter overflow. this flag will not be set if t0oe (tstat.0) is set. cleared by hardware when processor vectors to interrupt routine, or by clearing the bit in software. tcon.4 tr0 timer 0 run control bit. set/cleared by software to turn timer/counter 0 on/off. tcon.3 ie1 interrupt 1 edge flag. set by hardware when external interrupt edge detected. cleared when interrupt processed. tcon.2 it1 interrupt 1 type control bit. set/cleared by software to specify falling edge/low level triggered external interrupts. tcon.2 ie0 interrupt 0 edge flag. set by hardware when external interrupt edge detected. cleared when interrupt processed. tcon.0 it0 interrupt 0 type control bit. set/cleared by software to specify falling edge/tow level triggered external interrupts. figure 7. timer/counter(tcon) register 24 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA tf2 exf2 rclk0 tclk0 exen2 msb lsb tr2 c/t2 cp/rl2 bit addressable reset value:00h t2con address:418 bit symbol function t2con.7 tf2 timer 2 overflow flag. set by hardware on timer/counter overflow. must be cleared by software. tf2 will not be set when rclk0, rclk1, tclk0, tclk1 or t2oe=1. t2con.6 exf2 timer 2 external flag is set when a capture or reload occurs due to a negative transition on t2ex (and exen2 is set). this flag will cause a timer 2 interrupt when this interrupt is enabled. exf2 is cleared by software. t2con.5 rclk0 receive clock flag. t2con.4 tclk0 tr ansmit clock flag. rclk0 and tclk0 are used to select timer 2 overflow rate as a clock source for uart0 instead of timer t1. t2con.3 exen2 timer 2 external enable bit allows a capture or reload to occur due to a negative transition on t2ex. t2con.2 tr2 start = 1/stop=0 control for timer 2. t2con.1 c/t2 timer or counter select. 0 = internal timer 1 = external event counter (falling edge triggered) t2con.0 cp/rl2 capture/reload flag. if cp/rl2 & exen2 = 1 captures will occur on negative transitions of t2ex. if cp/rl2 = 0, exen2 = 1 auto reloads occur with either timer 2 overflows or negative transitions at t2ex. if rclk or tclk = 1 the timer is set to auto reload on timer 2 overflow, this bit has no effect. figure 8. timer/counter 2 control (t2con) register new timer-overflow toggle output in the xa, the timer module now has two outputs, which toggle on overflow from the individual timers. the same device pins that are used for the t0 and t1 count inputs are also used for the new overflow outputs. an sfr bit (tnoe in the tstat register) is associated with each counter and indicates whether port-sfr data or the over- flow signal is output to the pin. these outputs could be used in applications for generating variable duty cycle pwm outputs (changing the auto-reload register values). also variable frequency (osc/8 to osc/8,388,608) out- puts could be achieved by adjusting the prescaler along with the auto-reload register values. with a 30.0mhz os- cillator, this range would be 3.58hz to 3.75mhz. timer t2 timer 2 in the xa is a 16-bit timer/counter which can operate as either a timer or as an event counter. this is selected by c/t2 in the special function register t2con. upon timer t2 overflow/underflow, the tf2 flag is set, which may be used to generate an interrupt. it can be operated in one of three operating modes: auto-reload (up or down counting), capture, or as the baud rate gen- erator (for either or both uarts via sfrs t2mod and t2con). these modes are shown in table 4. capture mode in the capture mode there are two options which are se- lected by bit exen2 in t2con. if exen2 = 0, then timer 2 is a 16-bit timer or counter, which upon overflowing sets bit tf2, the timer 2 overflow bit. this will cause an interrupt when the timer 2 interrupt is enabled. if exen2 = 1, then timer 2 still does the above, but with the added feature that a 1-to-0 transition at external in- put t2ex causes the current value in the timer 2 regis- ters, tl2 and th2, to be captured into registers rcap2l and rcap2h, respectively. in addition, the transition at t2ex causes bit exf2 in t2con to be set. this will cause an interrupt in the same fashion as tf2 when the timer 2 interrupt is enabled. the capture mode is illus- trated in figure 11. 25 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA auto-reload mode (up or down counter) in the auto-reload mode, the timer registers are loaded with the 16-bit value in t2caph and t2capl when the count overflows. t2caph and t2capl are initialized by software. if the exen2 bit in t2con is set, the timer registers will also be reloaded and the exf2 flag set when a 1-to-0 transition occurs at input t2ex. the auto- reload mode is shown in figure 12. in this mode, timer 2 can be configured to count up or down. this is done by setting or clearing the bit dcen (down counter enable) in the t2mod special function register (see table 4). the t2ex pin then controls the count direction. when t2ex is high, the count is in the up direction, when t2ex is low, the count is in the down direction. figure 12 shows timer 2, which will count up automati- cally, since dcen = 0. in this mode there are two op- tions selected by bit exen2 in the t2con register. if exen2 =0, then timer 2 counts up to ffffh and sets the tf2 (overflow flag) bit upon overflow. this causes the timer 2 registers to be reloaded with the 16-bit value in t2capl and t2caph, whose values are preset by software. if exen2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1 -to-0 transition at input t2ex. this transition also sets the exf2 bit. if enabled, either tf2 or exf2 bit can generate the timer 2 inter- rupt. in figure 13, the dcen = 1; this enables the timer 2 to count up or down. in this mode, the logic level of t2ex pin controls the direction of count. when a logic "1" is applied at pin t2ex, the timer 2 will count up. the timer 2 will overflow at ffffh and set the tf2 flag, which can then generate an interrupt if enabled. this timer overflow, also causes the 16-bit value in t2capl and t2caph to be reloaded into the timer registers tl2 and th2, respec- tively. a logic "0" at pin t2ex causes timer 2 to count down. when counting down, the timer value is compared to the 16-bit value contained in t2caph and t2capl. when the value is equal, the timer register is loaded with ffff hex. the underflow also sets the tf2 flag, which can generate an interrupt if enabled. the external flag exf2 toggles when timer 2 underflows or overflows. this exf2 bit can be used as a 17th bit of resolution, if needed. the exf2 flag does not generate an interrupt in this mode. as the baud rate generator, timer t2 is incremented by tclk. baud rate generator mode by setting the tclkn and/or rclkn in t2con or t2mod, the timer 2 can be chosen as the baud rate generator for either or both uarts. the baud rates for transmit and receive can be simultaneously different. programmable clock-out a 50% duty cycle clock can be programmed to come out on p1 .6. this pin, besides being a regular i/o pin, has two alternate functions. it can be programmed (1) to input the external clock for timer/counter 2 or (2) to out- put a 50% duty cycle clock ranging from 3.58hz to 3.75mhz at a 30mhz operating frequency. to configure the timer/counter 2 as a clock generator, bit c/t2 (in t2con) must be cleared and bit t2oe in t2mod must be set. bit tr2 (t2con.2) also must be set to start the timer. the clock-out frequency depends on the oscillator fre- quency and the reload value of timer 2 capture registers (tcap2h, tcap2l) as shown in this equation: in the clock-out mode timer 2 roll-overs will net gener- ate an interrupt. this is similar to when it is used as a baud-rate generator. it is possible to use timer 2 as a baud-rate generator and a clock generator simultaneously. note, however, that the baud-rate will be 1/8 of the clock- out frequency. tclk 2 x (65536 - tcap2h, tcap2l) 26 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA table 4. timer 2 operating modes tr2 cp/rl2 rclk+tclk ocen mode 0 x x x timer oft (stopped) 1 0 0 0 16-bit auto-reload, counting up 1 0 0 1 16-bit auto-reload, counting up or down depending on t2ex pin 1 1 0 x 16-bitcapture 1 x 1 x baud rate generator ---- - - msb lsb t1oe t0oe t s tat bit addressable reset value:00h address:411 bit symbol function tstat.2 t1oe when 0, this bit allows the t1 pin to clock timer 1 when in the counter mode. when 1, t1 acts as an output and toggles at every timer 1 overflow. tstat.0 t0oe when 0, this bit allows the to pin to clock timer 0 when in the counter mode. when 1, t0 acts as an output and toggles at every timer 0 overflow. figure 9. timer 0 and 1 extended status (tstat) -- -- rclk1 tclk1 msb lsb t2oe dcen t2mod bit addressable reset value:00h address:419 bit symbol function t2mod.5 rclk1 receive clock flag. t2mod.4 tclk1 tr ansmit clock flag. rclk1 and tclk1 are used to select timer 2 overflow rate as a clock source for uart1 instead of timer t1. t2mod.1 t2oe when 0, this bit allows the t2 pin to clock timer 2 when in the counter mode. when 1, t2 acts as an output and toggles at every timer 2 overflow. t2mod.5 dcen controls count direction for timer 2 in autoreload mode. dcen=0 counter set to count up only dcen=1 counter set to count up or down, depending on t2ex (see text). figure 10. timer 2 mode control (t2mod) 27 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA tl2 (8-bits) t2capl capture control transition detector t2ex pin tr2 figure 11. timer 2 in capture mode tclk t2 pin c/t2=0 c/t2=1 th2 (8-bits) t2caph tf2 timer 2 interrupt exf2 control exen2 tl2 (8-bits) t2capl reload control transition detector t2ex pin tr2 figure 12. timer2 in auto-reload mode(decn=0) tclk t2 pin c/t2=0 c/t2=1 th2 (8-bits) t2caph tf2 timer 2 interrupt exf2 control exen2 28 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA control figure 13. timer 2 auto reload mode (dcen=1) tclk t2 pin c/t2=0 c/t2=1 tl2 tr2 t2capl th2 overflow tf2 exf2 toggle t2ex pin count direction 1=up 0=down interupt ffh ffh t2caph (up counting reload value) (down counting reload value) 29 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA watchdog timer the watchdog timer subsystem protects the system from incorrect code execution by causing a system reset when the watchdog timer underflows as a result of a failure of software to feed the timer prior to the timer reaching its terminal count. it is important to note that the watchdog timer is running after any type of reset and must be turned off by user software if the application does not use the watchdog function. watchdog function the watchdog consists of a programmable prescaler and the main timer. the prescaler derives its clock from the tclk source that also drives timers 0, 1, and 2. the watchdog timer subsystem consists of a programmable 13-bit prescaler, and an 8-bit main timer. the main timer is clocked (decremented) by a tap taken from one of the top 8-bits of the prescaler as shown in figure 14. the clock source for the prescaler is the same as tclk (same as the clock source for the timers). thus the main counter can be docked as often as once every 32 tclks (see table 5). the watchdog generates an underflow signal (and is autoloaded from wdl) when the watchdog is at count 0 and the clock to decrement the watchdog oc- curs. the watchdog is 8 bits wide and the autoload value can range from 0 to ffh. (the autoload value of 0 is permissible since the prescaler is cleared upon autoload). this leads to the following user design equations. defini- tions: t osc is the oscillator period, n is the selected prescaler tap value, w is the main counter autoload value, p is the prescaler value from table 5, t min is the mini- mum watchdog time-out value (when the autoload value is 0), t max is the maximum time-out value (when the autoload value is ffh), t d is the design time-out value. t min = t osc x 4 x 32 (w = 0, n = 4) t max = t osc x 64 x 4096 x 256 (w =255, n =64) t d = t osc x n x p x (w + 1) the watchdog timer is not directly loadable by the user. instead, the value to be loaded into the main timer is held in an autoload register. in order to cause the main timer to be loaded with the appropriate value, a special sequence of software action must take place. this op- eration is referred to as feeding the watchdog timer. to feed the watchdog, two instructions must be sequen- tially executed successfully. no intervening sfr ac- cesses are allowed, so interrupts should be disabled before feeding the watchdog. the instructions should move a5h to the wfeed1 register and then 5ah to the wfeed2 register. if wfeed1 is correctly loaded and wfeed2 is not correctly loaded, then an immediate watchdog reset will occur. the program sequence to feed the watchdog timer or cause new wdcon settings to take effect is as follows: clr ea ; disable global interrupts. mov.b wfeed1, #a5h ; do w atchdog feed part 1 mov.b wfeed2, #5ah ; do w atchdog feed part 2 setb ea ; re-enable global interrupts. this sequence assumes that the xa interrupt system is enabled and there is a possibility of an interrupt request occurring during the feed sequence. if an interrupt was allowed to be serviced and the service routine contained any sfr access, it would trigger a watchdog reset. if it is known that no interrupt could occur during the feed sequence, the instructions to disable and re-enable in- terrupts may be removed. the software must be written so that a feed operation takes place every t d seconds from the last feed opera- tion. some tradeoffs may need to be made. it is not ad- visable to include feed operations in minor loops or in subroutines unless the feed operation is a specific sub- routine. to turn the watchdog timer completely off, the following code sequence should be used: mov.b wdcon, #0 ; set wd control register to clear wdrun. mov.b wfeed1 , #a5h ; do watchdog feed part 1 mov.b wfeed2, #5ah ; do w atchdog feed part 2 this sequence assumes that the watchdog timer is be- ing turned off at the beginning of initialization code and that the xa interrupt system has not yet been enabled. if the watchdog timer is to be turned off at a point when interrupts may be enabled, instructions to disable and re-enable interrupts should be added to this sequence. watchdog control register (wdcon) the reset values of the wdgon and wdl registers will be such that the watchdog timer has a timeout period of 4 x 4096 x t osc and the watchdog is running. wdcon can be written by software but the changes only take effect after executing a valid watchdog feed sequence. 30 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA table 5. prescaler select values in wdcon pre2 pre1 pred divisor 00 0 32 00 1 64 0 1 0 128 0 1 1 256 1 0 0 512 1 0 1 1024 1 1 0 2048 1 1 1 4096 watchdog detailed operation when external reset is applied, the following takes place: ? watchdog run control bit set to on (1). ? autoload register wdl set to 00 (mm. count). ? watchdog time-out flag cleared. ? prescaler is cleared. ? prescaler tap set to the highest divide. ? autoload takes place. when coming out of a hardware reset, the software should load the autoload register and then feed the watchdog (cause an autoload). if the watchdog is running and happens to underflow at the time the external reset is applied, the watchdog time-out flag will be cleared. figure 14. watchdog timer in xa pre2 pre1 pre0 - - - wdrun wdtof wdcon internal reset prescaler tclk mov wfeed1,#a5h mov wfeed2,#5ah watchdog feed sequence 8-bit down counter wdl 31 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA when the watchdog underflows, the following action takes place (see figure 14): ? autoload takes place. ? watchdog time-out flag is set ? watchdog run bit unchanged. ? autoload (wdl) register unchanged. ? prescaler tap unchanged. ? all other device action same as external reset. note that if the watchdog underflows, the program counter will be loaded from the reset vector as in the case of an internal reset. the watchdog time-out flag can be exam- ined to determine if the watchdog has caused the reset condition. the watchdog time-out flag bit can be cleared by software. wdcon register bit definitions wdcon.7 pre2 prescaler select 2, reset to 1 wdcon.6 prel prescaler select 1, reset to 1 wdcon.5 pre0 prescaler select 0, reset to 1 wdcon.4 - wdcon.3 - wdcon.2 wdrun w atchdog run control bit, re set to 1 wdcon.1 wdtof time out flag wdcon.0 - uarts baud rate selection is somewhat different due to the clocking scheme used for the xa timers. some other enhancements have been made to uart operation. the first is that there are separate interrupt vectors for each uart s transmit and receive functions. the uart transmitter has been double buffered, allow- ing packed transmission of data with no gaps between bytes and less critical interrupt service routine timing. a break detect function has been added to the uart. this operates independently of the uart itself and provides a start-of-break status bit that the program may test. finally, an overrun error flag has been added to detect missed characters in the received data stream. the double buffered uart transmitter may require some software changes in code written for the original xa single buffered uart. each uart baud rate is determined by either a fixed division of the oscillator (in uart modes 0 and 2) or by the timer 1 or timer 2 overflow rate (in uart modes 1 and 3). timer 1 defaults to clock both uarto and uart1. timer 2 can be programmed to clock either uart0 through t2con (via bits r0clk and t0clk) or uart1 through t2mod (via bits r1clk and t1 clk). in this case, the uart not clocked by t2 could use t1 as the clock source. the serial port receive and transmit registers are both accessed at special function register snbuf writing to snbuf loads the transmit register, and reading snbuf accesses a physically separate receive register. the serial port can operate in 4 modes: mode 0: serial i/o expansion mode. serial data enters and exits through rxdn. txdn outputs the shift clock. 8 bits are transmitted/received (lsb first). (the baud rate is fixed at 1/16 the oscillator frequency.) mode 1: standard 8-bit uart mode. 10 bits are transmitted(through txdn) or received (through rxdn): a start bit (0), 8 data bits (lsb first), and a stop bit (1). on receive, the stop bit goes intorb8 in special function register sncon. the baud rate is variable. mode 2: fixed rate 9-bit uart mode. 11 bits are trans- mitted (through txd) or received (through rxd): start bit (0), 8 data bits (lsb first), a programmable 9th data bit, and a stop bit (1). on transmit, the 9th data bit tb8_n in sncon) can be assigned the value of 0 or 1. or, for example, the parity bit (p, in the psw) could be moved into tb8_n. on receive, the 9th data bit goes into rb8_n in special function register sncon, while the stop bit is ignored. the baud rate is programmable to 1/32 of the oscillator frequency. mode 3: standard 9-bit uart mode. 11 bits are trans- mitted (through txdn) or received (through rxdn): a start bit (0), 8 data bits (lsb first), a programmable 9th data bit, and a stop bit (1). in fact, mode 3 is the same as mode 2 in all respects except baud rate. the baud rate in mode 3 is variable. in all four modes, transmission is initiated by any in- struction that uses snbuf as a destination register. re- ception is initiated in mode 0 by the condition ri_n = 0 and ren_n = 1. reception is initiated in the other modes by the incoming start bit if ren_n = 1. 32 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA serial port control register the serial port control and status register is the special function register sncon, shown in figure 16. this reg- ister contains not only the mode selection bits, but also the 9th data bit for transmit and receive (tb8_n and rb8_n), and the serial port interrupt bits ti_n and ri_n). ti flag in order to allow easy use of the double buffered uart transmitter feature, the ti_n flag is set by the uart hard- ware under two conditions. the first condition is the completion of any byte transmission. this occurs at the end of the stop bit in modes 1, 2, or 3, or at the end of the eighth data bit in mode 0. the second condition is when snbuf is written while the uart transmitter is idle. in this case, the ti_n flag is set in order to indicate that the second uart transmitter buffer is still avail- able. typically, uart transmitters generate one interrupt per byte transmitted. in the case of the xa uart, one addi- tional interrupt is generated as defined by the stated con- ditions for setting the ti_n flag. this additional interrupt does not occur if double buffering is bypassed as ex- plained below. note that if a character oriented approach is used to transmit data through the uart; there could be a second interrupt for each character transmitted, depending on the timing of the writes to sbuf. for this reason, it is generally better to bypass double buffering when the uart transmitter is used in character oriented mode. this is also true if the uart is polled rather than interrupt driven, and when transmission is character ori- ented rather than message or string oriented. the inter- rupt occurs at the end of the last byte transmitted when the uart becomes idle. among other things, this allows a program to determine when a message has been trans- mitted completely. the interrupt service routine should handle this additional interrupt. the recommended method of using the double buffering in the application program is to have the interrupt ser- vice routine handle a single byte for each interrupt oc- currence. in this manner the program essentially does not require any special considerations for double buffer- ing. unless higher priority interrupts cause delays in the servicing of the uart transmitter interrupt, the double buffering will result in transmitted bytes being tightly packed with no intervening gaps. 9-bit mode please note that the ninth data bit (tb8) is not double buffered. care must be taken to insure that the tb8 bit contains the intended data at the point where it is trans- mitted. double buffering of the uart transmitter may be bypassed as a simple means of synchronizing tb8 to the rest of the data stream. bypassing double buffering the uart transmitter may be used as if it is single buff- ered. the recommended uart transmitter interrupt ser- vice routine (isr) technique to bypass double buffering first clears the ti_n flag upon entry into the isr, as in standard practice. this clears the interrupt that activated the isr. secondly, the ti_n flag is cleared immediately following each write to snbuf. this clears the interrupt flag that would otherwise direct the program to write to the second transmitter buffer. if there is any possibility that a higher priority interrupt might become active be- tween the write to snbuf and the clearing of the ti_n flag, the interrupt system may have to be temporarily disabled during that sequence by clearing, then setting the ea bit in the iel register. 33 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA clocking scheme/baud rate generation the xa uarts clock rates are determined by either a fixed division (modes 0 and 2) of the oscillator clock or by the timer 1 or timer 2 overflow rate (modes 1 and 3). the clock for the uarts in xa runs at 1 6x the baud rate. if the timers are used as the source for baud clock, since maximum speed of timers/baud clock is osc/4, the maximum baud rate is timer overflow divided by 16 i.e. osc/64. in mode 0, it is fixed at osc/1 6. in mode 2, however, the fixed rate is osc/32. pre-scaler 00 osc/4 for all timers t0, 1, 2, 01 osc/16 controlled by pt1, pt0 10 osc/64 bits in scr 11 reserved baud rate for uart mode 0: baud_rate = osc/16 baud rate calculation for uart mode 1 and 3: baud_rate = timer_rate/16 timer_rate =osc/(n*(timer_range- timer_reload_value)) where n = the tclk prescaler value: 4,16, or 64. and timer_range = 256 for timer 1 in mode 2. 65536 for timer 1 in mode 0 and timer 2 in count up mode. the timer reload value may be calculated as follows: timer_reload_value = timer_range(osc/ (baud_rate*n*1 6)) notes: 1.the maximum baud rate for a uart in mode 1 or 3 is osc/64. 2.the lowest possible baud rate (for a given oscillator frequency and n value) may be found by using a timer reload value of 0. 3.the timer reload value may never be larger than the timer range. 4.if a timer reload value calculation gives a negative or fractional result, the baud rate requested is not pos- sible at the given oscillator frequency and n value. baud rate for uart mode 2: baud_rate = osc/32 using timer 2 to generate baud rates timer t2 is a 16-bit up/down counter in xa. as a baud rate generator, timer 2 is selected as a clock source for either/both uart0 and uart1 transmitters and/or re- ceivers by setting tclkn and/or rclkn in t2con and t2mod. as the baud rate generator, t2 is incremented as osc/n where n = 4, 16 or 64 depending on tclk as programmed in the scr bits pt1, and pto. so, if t2 is the source of one uart, the other uart could be clocked by either t1 overflow or fixed clock, and the uarts could run independently with different baud rates. t2con bit5 bit4 0x418 rclk0 tclk0 t2mod bit5 bit4 0x419 rclk1 tclk1 scr bit3 bit2 0x440 pt1 pt0 prescaler select for timer clock (tclk) 34 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA - -- - fen brn msb lsb oen stintn bit addressable reset value:00h s1stat 425 snstataddress: s0stat 421 bit symbol function snstat.3 fen fr aming error flag is set when the receiver fails to see a valid stop bit at the end of the frame. cleared by software. snstat.2 brn break detect flag is set if a character is received with all bits (including stop bit) being logic 0. thus it gives a start of break detect on bit 8 for mode 1 and bit 9 for modes 2 and 3. the break detect feature operates independently of the uarts and provides the start of break detect status bit that a user program may poll. cleared by software. snstat.1 oen overrun error flag is set if a new character is received in the receiver buffer while it is still full (before the software has read the previous character from the buffer), i.e., when bit 8 of a new byte is received while ri in sncon is still set. cleared by software. snstat.0 stintn this flag must be set to enable any of the above status flags to generate a receive interrupt (rln). the only way it can be cleared is by a software write to this register. figure 15. serial port extended status (snstat) register (see also figure 17 regarding framing error flag) interrupt scheme there are separate interrupt vectors for each uart s transmit and receive functions. table 6. vector locations for uarts in xa vector address interrupt source arbitration a0h - a3h uart 0 receiver 7 a4h - a7h uart 0 transmitter 8 a8h - abh uart i receiver 9 ach-afh uarti t ransmitter 10 note: the transmit and receive vectors could contain the same isr address to work like a 8051 interrupt scheme error handling, status rags and break detect the uarts in xa has the following error flags; see fig- ure 15. multiprocessor communications modes 2 and 3 have a special provision for multiproces- sor communications. in these modes, 9 data bits are received. the 9th one goes into rb8. then comes a stop bit. the port can be programmed such that when the stop bit is received, the serial port interrupt will be acti- vated only if rb8 = 1. this feature is enabled by setting bit sm2 in scon. a way to use this feature in multipro- cessor systems is as follows: when the master processor wants to transmit a block of data to one of several slaves, it first sends out an ad- dress byte which identifies the target slave. an address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. with sm2 = 1, no slave will be interrupted by a data byte. an address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. the addressed slave will clear its sm2 bit and prepare to receive the data bytes that will be coming. the slaves that werent being addressed leave their sm2s set and go on about their business, ignoring the coming data bytes. sm2 has no effect in mode 0, and in mode 1 can be used to check the validity of the stop bit although this is better done with the framing error (fe) flag. in a mode 1 reception, if sm2 = 1, the receive interrupt will not be activated unless a valid stop bit is received. 35 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA automatic address recognition automatic address recognition is a feature which al- lows the uart to recognize certain addresses in the serial bit stream by using hardware to make the com- parisons. this feature saves a great deal of software overhead by eliminating the need for the software to ex- amine every serial address which passes by the serial port. this feature is enabled by setting the sm2 bit in scon. in the 9 bit uart modes, mode 2 and mode 3, the receive interrupt flag (ri) will be automatically set when the received byte contains either the "given" ad- dress or the broadcast address. the 9 bit mode re- quires that the 9th information bit is a 1 to indicate that the received information is an address and not data. automatic address recognition is shown in figure 18. using the automatic address recognition feature allows a master to selectively communicate with one or more slaves by invoking the given slave address or addresses. all of the slaves may be contacted by using the broad- cast address. two special function registers are used to define the slave s address, saddr, and the address mask, saden. saden is used to define which bits in the sad dr are to be used and which bits are dont care. the saden mask can be logically anded with the sad dr to create the given address which the master will use for addressing each of the slaves. use of the given address allows multiple slaves to be recog- nized while excluding others. the following examples will help to show the versatility of this scheme: siave0 saddr =1100 0000 saden = 1111 1101 given =1100 00x0 slavel saddr =1100 0000 saden = 1111 1110 given =1100 000x in the above example saddr is the same and the sad en data is used to differentiate between the two slaves. slave 0 requires a 0 in bit 0 and it ignores bit 1. slave 1 requires a 0 in bit 1 and bit 0 is ignored. a unique ad- dress for slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. a unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). thus, both could be addressed with 1100 0000. in a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: slave0 saddr =1100 0000 saden = 1111 1001 given =1100 0xx0 slave 1 saddr =1110 0000 saden = 1111 1010 given =1110 0x0x siave2 saddr =1110 0000 saden = 1111 1100 given =1110 00xx in the above example the differentiation among the 3 slaves is in the lower 3 address bits. slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. to select slaves 0 and 1 and exclude slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2. the broadcast address for each slave is created by tak- ing the logical or of saddr and saden. zeros in this result are tested as dont-cares. in most cases, inter- preting the dont-cares as ones, the broadcast address will be ff hexadecimal. upon reset saddr and saden are loaded with os. this produces a given address of all dont cares as well as a broadcast address of all dont cares. this effec- tively disables the automatic addressing mode and al- lows the microcontroller to use standard uart drivers which do not make use of this feature. 36 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA where sm0, sm1, specify the serial port mode, as bollows: sm0 sm1 mode description baud rate 0 0 0 shift register f osc /16 0 1 1 8-bit uart variable 1 0 2 9-bit uart f osc /32 1 1 3 9-bit uart variable bit symbol function sncon.5 sm2 enables the multiprocessor communication feature in modes 2 and 3. in mode 2 or 3, if sm2 is set to 1, then ri will not be activated it the received 9th data bit (rb8) is 0. in mode 1, it sm2=1 then ri will not be activated if a valid stop bit was not received. in mode 0, sm2 should be 0. sncon.4 ren enables serial reception. set by software to enable reception. clear by software to disable reception. sncon.3 tb8 the 9th data bit that will be transmitted in modes 2 and 3. set or clear by software as desired. the tb8 bit is not double buffered. see text for details. sncon.2 rb8 in modes 2 and 3, is the 9th data bit that was received. in mode 1, it sm2=0, rb8 is the stop bit that was received. in mode 0, rb8 is not used. sncon.1 ti tr ansmit interrupt flag. set when another byte may be written to the uart transmit- ter. see text for details. must be cleared by software. sncon.0 ri receive interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or at the end of the stop bit time in the other modes (except see sm2). must be cleared by software. sm0 sm1 sm2 ren tb8 msb lsb rb8 ti ri bit addressable reset value:00h sncon address:s0con 420 s1con 424 figure 16. serial port control (sncon) register stintn snstat if 0, sets fe oen brn fen - - - - start bit d0 d1 d2 d3 d4 d5 d6 d7 d8 only in mode 2,3 data byte stop bit figure 17. uart framing error detection 37 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA ri_n sncon ti_n rb8_n tb8_n ren_n sm2_n sm1_n sm0_n 1 1 1 0 11x comparator received address d0 to d7 programmed address in uart mode 2 or mode 3 and sm2=1: interrupt if ren=1, rb8=1 and "received address" = "programmed address" -when own address received, clear sm2 to received data bytes -when all data bytes have been received:set sm2 to wait for next address d0 d1 d2 d3 d4 d5 d6 d7 d8 figure 18. uart multiprocessor communication, automatic address recognition 38 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA i/o port output configuration each i/o port pin can be user configured to one of 4 output types. the types are quasi-bidirectional (essen- tially the same as standard 80c51 family i/o ports), open-drain, push-pull, and off (high impedance). the default configuration after reset is quasi-bidirectional. however, in the rom less mode (the ea pin is low at reset), the port pins that comprise the external data bus will default to push-pull outputs. i/o port output configurations are determined by the set- tings in port configuration sfrs. there are 2 sfrs for each port, called pncfga and pncfgb, where n is the port number. one bit in each of the 2 sfrs relates to the output setting for the corresponding port pin, allow- ing any combination of the 2 output types to be mixed on those port pins. for instance, the output type of port 1 pin 3 is controlled by the setting of bit 3 in the sfrs p1cfga and p1cfgb. table 7 shows the configuration register settings for the 4 port output types. the electrical characteristics of each output type may be found in the dc characteristic table. table 7. port configuration register settings pncfgb pncfga port output mode 0 0 open drain 0 1 quasi-bidirectional 1 0 off (high impedance) 1 1 push-pull note: mode changes may cause glitches to occur during tran- sitions. when modifying both registers, write instruc- tions should be carried out consecutively. external bus the external program/data bus allows for 8-bit or 16-bit bus width, and address sizes from 12 to 20 bits. the bus width is selected by an input at reset (see reset op- tions below), while the address size is set by the pro- gram in a configuration register. if all off-chip code is selected (through the use of the ea pin), the initial code fetches will be done with the maximum address size (20 bits). reset the device is reset whenever a logic "0" is applied to rst for at least 10 microseconds, placing a low level on the pin re-initializes the on-chip logic. reset must be asserted when power is initially applied to the xa and held until the oscillator is running. the duration of reset must be extended when power is initially applied or when using reset to exit power down mode. this is due to the need to allow the oscillator time to start up and stabilize. for most power supply ramp up conditions, this time is 10 milliseconds. as rst is brought high again, an exception is generated which causes the processor to jump to the reset address. typically, this is the address contained in the memory location 0000. the destination of the reset jump must be located in the first 64k of code address on power-up, all vectors are 16-bit values and so point to page zero ad- dresses only. after a reset the ram contents are inde- terminate. alternatively, the boot vector may supply the reset ad- dress. this happens when use of the boot vector is forced or when the flash status byte is non-zero. these cases are described in the section hardware activation of the boot v ector on page 10. some typical values for a and c: r=100k, c=1.0uf r=1.0m, c=0.1uf (assuming that the vdd rise time is 1ms or less) xa vdd r c reset figure 19. recommended reset circuit 39 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA reset options the ea pin is sampled on the rising edge of the rst pulse, and determines whether the device is to begin execution from internal or external code memory. ea pulled high configures the xa in single-chip mode. if ea is driven low, the device enters romless mode. after reset is released, the ea/wait pin becomes a bus wait signal for external bus transactions. the busw/p3.5 pin is weakly pulled high while reset is asserted, allowing simple biasing of the pin with a resis- tor to ground to select the altermate bus width. if the busw pin is not driven at reset, the weak pullup will causes 1 to be loaded for the bus width, giving a 16-bit external bus. busw may be pulled low with a 2.7k or smaller value resistor, giving an 8-bit external bus. the bus width setting from the busw pin may be overridden by software once the user program is running. both ea and busw must be held for three oscillator clock times after reset is deasserted to guarantee that their values are latched correctly. power reduction modes the xa supports idle and power down modes of power reduction. the idle mode leaves some peripherals run- ning to allow them to wake up the processor when an interrupt is generated. the power down mode stops the oscillator in order to minimize power. the processor can be made to exit power down mode via reset or one of the external interrupt inputs. in order to use an external inter- rupt to re-activate the xa while in power down mode, the external interrupt must be enabled and be configured to level sensitive mode. in power down mode, the power supply voltage may be reduced to the ram keep-alive voltage (2v), retaining the ram, register, and sfr val- ues at the point where the power down mode was en- tered. interrupts the xa supports 38 vectored interrupt sources. these include 9 maskable event interrupts, 7 exception inter- rupts, 16 trap interrupts, and 7 software interrupts. the maskable interrupts each have 8 priority levels and may be globally and/or individually enabled or disabled. the xa defines tour types of interrupts: ? exception interrupts - these are system level errors and other very important occurrences which include stack overflow, divid-by-0, and reset. ? event interrupts - these are peripheral interrupts from devices such as uarts, timers, and external interrupt inputs. ? software interrupts - these are equivalent of hard- ware interrupt, but are requested only under software control. ? trap interrupts - these are trap instructions, gener- ally used to call system services in a multi-tasking sys- tem. exception interrupts, software interrupts, and trap inter- rupts are generally standard for xa derivatives and are detailed in the xa user guide. event interrupts tend to be different on different xa derivatives. the xa supports a total of 9 maskable event interrupt sources (for the various xa peripherals), seven software interrupts, 5 exception interrupts (plus reset), and 16 traps. the maskable event interrupts share a global interrupt disable bit (the ea bit in the iel register) and each also has a separate individual interrupt enable bit (in the iel or ieh registers). only three bits of the ipa register val- ues are used on the xa. each event interrupt can be set to occur at one of 8 priority levels via bits in the interrupt priority (ip) registers, ipa0 through ipa5. the value 0 in the ipa field gives the interrupt priority 0, in effect dis- abling the interrupt. a value of 1 gives the interrupt a priority of 9, the value 2 gives priority 10, etc. the result is the same as if all four bits were used and the top bit set for all values except 0. the complete interrupt vector list for the xa, including all 4 interrupt types, is shown in the following tables. the tables include the address of the vector for each inter- rupt, the related priority register bits (if any), and the ar- bitration ranking for that interrupt source. the arbitration ranking determines the order in which interrupts are pro- cessed if more than one interrupt of the same priority occurs simultaneously. 40 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA table 8. interrupt vectors exception/traps precedence description vector address arbitration ranking reset (h/w, watchdog, s/w) 0000-0003 0 (high) breakpoint (h/w trap 1) 0004-0007 1 trace (h/w trap 2) 0008-000b 1 stack overflow (h/w trap 3) 000c-000f 1 divide by 0 (h/w trap 4) 0010-0013 1 user reti (h/w trap 5) 0014-0017 1 trap 0-15 (software) 0040-007f 1 event interrupts description flag bit vector arbitration address enable bit interrupt priority ranking external interrupt 0 le0 0080-0083 ex0 lp a0.2-0 (px0) 2 timer 0 interrupt tf0 0084-0087 et0 ip a0.6-4 (pt0) 3 external interrupt 1 ie1 0088-008b ex1 ip al.2-0 (px1) 4 timer 1 interrupt tf1 008c-008f et1 lp a1.6-4 (pt1) 5 timer 2 interrupt tf2(exf2) 0090-0093 et2 lp a2.2-0(pt2) 6 serial port 0 rx ri.0 00a0-00a3 eri0 lpa4.2-0(prio) 7 serial port 0 tx ti.0 00a4-00a7 eti0 lpa4.6-4 (ptio) 8 serial port 1 rx ri.1 00a8-00ab eri1 lpa5.2-0(prt1) 9 serial port 1 tx ti.1 ooac -00af eti1 lpa5.6-4(pti1) 10 software interrupts description flag bit vector address enable bit interrupt priority software interrupt 1 swr1 0100-0103 swe1 (fixed at 1) software interrupt 2 swr2 0104-0107 swe2 (fixed at 2) software interrupt 3 swr3 0108-010b swe3 (fixed at 3) software interrupt 4 swr4 010c-010f swe4 (fixed at 4) software interrupt 5 swr5 0110-0113 swes (fixed at 5) software interrupt 6 swr6 0114-0117 swe6 (fixed at 6) software interrupt 7 swr7 0118-011b swe7 (fixed at 7) 41 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA absolute maximum ratings parameter ra ting unit operating temperature under bias -55 to + 125 c storage temperature range -65 to + 150 c voltage on ea/v pp pin to v ss 0 to + 13.0 v voltage on any other pin to v ss 0.5 to v dd + 0.5v v maximum i ol per i/o pin 15 ma power dissipation (based on package heat transfer limitations, not device 1.5 w power consumption) dc electrical characteristics v dd = 4.5v to 5.5v unless otherwise specified; t amb = 0 to + 70 c for commercial symbol parameter test conditions limits unit min typ max supplies i dd supply current operating 5.5v, 30 mhz 110 ma i id idle mode supply current 5.5v, 30 mhz 32 ma i pd power-down current 30 ua i pdi power-down current 150 ua v ram ram-keep-alive voltage ram-keep-alive voltage 1.5 v v il input low voltage -0.5 0.22v dd v v ih input high voltage, except xtal1, rst at 5.0v 2.2 v v ih1 input high voltage to xtal1, rst at 5.0v 0.7v dd v v ol output low voltage all ports, ale, ps en 3 i ol =3.2ma, v dd =5.0v 0.5 v v oh1 output high voltage all ports, ale, psen 1 i oh =-100ua, v dd =4.5v 2.4 v v oh2 output high voltage, ports p0-3, ale, psen 2 i oh =3.2ma, v dd =4.5v 2.4 v c io input/output pin capacitance 15 pf i il logical 0 input current, p0-3 6 v in = 0.45v -25 -75 ua i li input leakage current, p0-3 5 v in = v il or v ih +10 ua i tl logical 1 to 0 transition current all ports 4 at 5.5v -650 ua 42 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA notes: 1.ports in quasi bi-directional mode with weak pull-up (applies to ale, psen only during reset). 2.ports in push-pull mode, both pull-up and pull-down assumed to be same strength. 3.in all output modes. 4.port pins source a transition current when used in quasi-bidirectional mode and externally driven from 1 to 0. this current is highest when v in is approximately 2v. 5.measured with port in high impedance output mode. 6.measured with port in quasi-bidirectional output mode. 7.load capacitance for all outputs=80pf 8.under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 1 5ma (*note: this is 85 c specification for v dd = 5v.) maximum i ol per 8-bit port: 26ma maximum total i ol for all output: 71 ma if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 43 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA ac electrical characeristics (5v) vdd = 4.5v to 5.5v; tamb = 0 to +70 c for commercial symbol figure parameter variable clock unit min max external clock f c 26 oscillator frequency 0 30 mhz t c 26 clock period and cpu timing cycle 1/ f c ns t chcx 26 clock high time t c * 0.5 7 ns t clcx 26 clock low time t c * 0.4 7 ns t clch 26 clock rise time 5 ns t chcl 26 clock fall time 5 ns address cycle t crar 25 delay from clock rising edge to ale rising edge 10 46 ns t lhll 20 ale pulse width (programmable) (v1 * t c )-6 ns t avll 20 address valid to ale de-asserted (set-up) (v1 * t c )-12 ns t llax 20 address hold after ale de-asserted (t c /2)-10 ns code read cycle t plph 20 psen pulse width (v2 * t c )-10 ns t llpl 20 ale de-asserted to psen asserted (t c /2)-7 ns t aviva 20 address valid to instruction valid, ale cycle (v3 * t c )-36 ns (access time) t avivb 21 address valid to instruction valid, non-ale cycle (v4 * t c )-29 ns (access time) t cpliv 20 psen asserted to instruction valid (v2 * t c )-29 ns (enable time) t pxix 20 instruction hold after psen de-asserted 0 ns t pxiz 20 bus 3-state after psen de-asserted t c - 8 ns (disable time) t ixua 20 hold time of unlatched part of address after 0 ns instruction latched data read cycle t rlrh 22 rd pulse width (v7 * t c )-10 ns t llrl 22 ale de-asserted to rd asserted (t c /2)-7 ns t avdva 22 address valid to data input valid, ale cycle (v6 * t c )-36 ns (access time) t avdvb 23 address valid to data input valid, non-ale cycle (v5 * t c )-29 ns (access time) t rldv 22 rd low to valid data in, enable time (v7 * t c )-29 ns t rhdx 22 data hold time after rd de-asserted 0 ns t rhdz 22 bus 3-state after rd de-asserted (disable time) t c -8 ns t dxua 22 hold time of unlatched part of address after 0 ns data latched 44 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA symbol figure parameter v ariable clock unit min max data write cycle t wlwh 24 wr pulse width (v8 * t c )-10 ns t llwl 24 ale falling edge to wr asserted (v12 * t c )-10 ns t qvwx 24 data valid before wr asserted (data setup time) (v13 * t c )-22 ns t whqx 24 data hold time after wr de-asserted (note 6) (v11 * t c )-5 ns t avwl 24 address valid to wr asserted (address setup time) (v9 * t c )-22 ns (note 5) t uawh 24 hold time of unlatched part of address after wr (v11 * t c )-7 ns is de-asserted wait input t wth 25 wait stable after bus strobe (v10*t c )-30 ns (rd,wr,or psen) asserted t wtl 25 wait hold after bus strobe (v10 * t c )-5 ns (rd,wr,or psen) asserted notes: 1.load capacitance for all outputs = 80p f. 2.variables v1 through v13 reflect programmable bus timing, which is programmed via the bus timing registers (btrh and btrl). refer to the xa user guide for details of the bus timing settings. v1) this variable represents the programmed width of the ale pulse as determined by the alew bit in the btrl register. v1 = 0.5 if the alew bit = 0, and 1.5 if the alew bit = 1. v2) this variable represents the programmed width of the psen pulse as determined by the cr1 and cr0 bits or the cral, cra0, and alew bits in the btrl register. - for a bus cycle with no ale, v2 = l if cr1/0 = 00, 2 if cr1/0 = 01, 3 if cr1/0 = 10, and 4 if cr1/0 = 11. note that during burst mode code fetches, psen does not exhibit transitions at the boundaries of bus cycles. v2 still applies for the purpose of determining peripheral timing requirements. - for a bus cycle with an ale, v2 = the total bus cycle duration (2 if cra1/0 = 00, 3 if cra1/0 = 01, 4 if cra1/0 = 10, and 5 if cra1/0 = 11) minus the number of clocks used by ale (v1 + 0.5). example: if cra1/0 = 10 and alew = 1, the v2 = 4 - (1.5 + 0.5) = 2. v3) this variable represents the programmed length of an entire code read cycle with ale. this time is deter mined by the cra1 and cra0 bits in the btrl register. v3 = the total bus cycle duration (2 if cra1/0 =00, 3 if cra1/0 =01, 4 if cra1/0 = 10, and 5 it cra1/0 = 11). v4) this variable represents the programmed length of an entire code read cycle with no ale. this time is determined by the cr1 and cr0 bits in the btrl register. v4 = 1 if cr1/0 = 00,2 if cr1/0= 01,3 if cr1/0= 10, and 4 if cr1/0 = 11. v5) this variable represents the programmed length of an entire data read cycle with no ale. this time is determined by the dr1 and dr0 bits in the btrh register. v5 = l if dr1/0 = 00,2 if dr1/0 = 01,3 if dr1/0 = 10, and 4 it dr1/0 = 11. v6) this variable represents the programmed length of an entire data read cycle with ale. the time is determined by the dra1 and dra0 bits in the btrh register. v6 = the total bus cycle duration (2 if dra1/0 = 00, 3 if dra1/0 = 01, 4 if dra1/0 = 10, and 5 if dra1/0 = 11). v7) this variable represents the programmed width of the rd pulse as determined by the dr1 and dr0 bits or the dra1, dra0 in the btrh register, and the alew bit in the btrl register. note that during a 16-bit operation on an 8-bit external bus, rd remains low and does not exhibit a transition between the first and second byte bus cycles. v7still applies for the purpose of determining peripheral timing requirements. the timing for the first byte is for a bus cycle with ale, the timing for the second byte is for a bus cycle with no ale. 45 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA - for a bus cycle with no ale, v7 = l if dr1/0 = 00, 2 if dr1/0 = 01,3 if dr1/0 = 10, and 4 if dr1/0 = 11. - for a bus cycle with an ale, v7 = the total bus cycle duration (2 it dr1/0 = 00, 3 if dra1/0 = 01, 4 if dra1/0 = 10, and s if dra1/0 = 11) minus the number of clocks used by ale (v1 + 0.5). example: if dra1/0 = 00 and alew = 0, then v7=2 - (0.5 + 0.5) = 1. v8) this variable represents the programmed width of the wrl and/or wrh pulse as determined by the wm1 bit in the btrl register. v8 1 if wm1 =0,and2 if wm1 =1. v9) this variable represents the programmed address setup time for a write as determined by the data write cycle duration (defined by dw1 and dw0 or the dwa1 and dwa0 bits in the btrh register), the wm0 bit in the btrl register, and the value of v8. - for a bus cycle with an ale, v9 = the total bus write cycle duration (2 if dwa1/0 = 00, 3 if dwa1/0 = 01, 4 if dwa1/ 0 = 10, and 5 if dwa1/0= 11) minus the number of clocks used by the wrl and/or wrh pulse (v8), minus the number of clocks used by data hold time (0 if wm0= 0 and l if wm0 = 1). example: if dwa1/0=10,wm0= 1, and wm1 =1, then v9=4-1 -2=1. - for a bus cycle with no ale, v9 = the total bus cycle duration (2 if dw1/0 = 00, 3 if ow1/0 = 01, 4 if dw1/0 = 10, and 5 if dw1/0 = 11) minus the number of clocks used by the wrl and/or wrh pulse (v8), minus the number of clocks used by data hold time (0 if wm0 = 0 and l if wm0 = 1). example: if dw1/0=11, wm0=1, and wm1 =0, then v9=5-1 -1=3. v10) this variable represents the length of a bus strobe for calculation of wait setup and hold times. the strobe may be rd (for data read cycles), wrl and/or wrh (for data write cycles), or psen (for code read cycles), depending on the type of bus cycle being widened by wait. v10 = v2 for wait associated with a code read cycle using psen v10 = v8 for a data write cycle using wrl and/or wrh. v10 = v7-1 for a data read cycle using rd. this means that a single clock data read cycle cannot be stretched using wait. if wait is used to vary the duration of data read cycles, the rd strobe width must be set to be at least two clocks in dura- tion. also see note 4. v11) this variable represents the programmed write hold time as determined by the wm0 bit in the btrl register. v11=0 if the wm0 bit=0, and 1 if the wm0 bit=1. v12) this variable represents the programmed period between the end of the ale pulse and the beginning of the wrl and/or wrh pulse as determined by the data write cycle duration (defined by the dwa1 and dwa0 bits in the btrh register), the wm0 bit in the btrl register, and the values of v1 and v8. v12= the total bus cycle duration (2 if dwa1/0 =00, 3 if dwa1/0 = 01, 4 it dwa1/0 = 10, and 5 it dwa1/0 = 11) minus the number of clocks used by the wrl and/or wrh pulse (v8), minus the number of clocks used by data hold time (0 if wm0 = 0 and lit wm0 = 1), minus the width of the ale pulse (v1). example:if dwa1/0= 11,wm0=1,wm1 =0, and alew =1, then v12=5-1 -1-1.5=1.5. v13) this variable represents the programmed data setup time for a write as determined by the data write cycle duration (defined by dw1 and dw0 or the dwa1 and dwa0 bits in the btrh register), the wm0 bit in the btrl register, and the values of v1 and v8. - for a bus cycle with an ale, v13 = the total bus cycle duration (2 if dwa1/0 = 00, 3 it dwa1/0 = 01, 4 if dwa1/0 = 10, and 5 if dwa1/0 = 11) minus the number of clocks used by the wrl and/or wrh pulse (v8), minus the number of clocks used by data hold time (0 if wm0 = 0 and 1 if wm0 = 1), minus the number of clocks used by ale (v1 + 0.5). example:if dwa1/0= 11, wm0=1, wm1 =1, and alew=0,then v13=5-1-2-1= 1. -for a bus cycle with no ale, v13 = the total bus cycle duration (2 if dw1/0 = 00, 3 if dw1/0 = 01, 4 it dw1/ 0 = 10, and 5 if dw1/0= 11) minus the number of clocks used by the wrl and/or wrh pulse (v8), minus the number of clocks used by data hold time (0 if wm0 = 0 and 1 if wm0 = 1). example:if dw1/0=01, wm0=1, and wm1 =0, then v13=3 -1 -1=1. 3. not all combinations of bus timing configuration values result in valid bus cycles. please refer to the xa user guide section on the external bus for details. 4.when code is being fetched for execution on the external bus, a burst mode fetch is used that does not have psen edges in every fetch cycle. thus, it wait is used to delay code fetch cycles, a change in the low order address lines must be detected to locate the beginning of a cycle. this would be a3-a0 for an 8-bit bus, and a3-a1 for a 16-bit bus. also, a 16-bit data read operation conducted on a 8-bit wide bus similarly does not include two separate rd strobes. so, a rising edge on the low order address line (a0) must be used to trigger a wait in the second halt of such a cycle. 46 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA 5.this parameter is provided for peripherals that have the data clocked in on the tailing edge of the wr strobe. this is not usually the case, and in most applications this parameter is not used. 6.please note that the xa requires that extended data bus hold time (wm0 = 1) to be used with external bus write cycles. 7.applies only to an external clock source, not when a crystal or ceramic resonator is connected to the xtal1 and xta12 pins. a4-a11 or a4-a19 * instr in is either d0-d7 or d0-d15, depending on the bus width (8 or 16 bits). figure 20. external program memory read cycle (ale cycle) a0 or a1-3, a12-19 instr in* ale psen multiplexed address and data unmultiplexed address t lhll t avll t llpl t llax t pliv t aviva t plph t pxiz t ixua t pxix a4-a11 or a4-a19 * instr in is either d0-d7 or d0-d15, depending on the bus width (8 or 16 bits). figure 21. external program memory read cycle (non-ale cycle) a0 or a1-3, a12-19 a0 or a1-a3, a12-19 instr in* ale psen multiplexed address and data unmultiplexed address t avivb 47 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA a4-a11 or a4-a19 * instr in is either d0-d7 or d0-d15, depending on the bus width (8 or 16 bits). figure 22. external data memory read cycle (ale cycle) a0 or a1-a3, a12-19 instr in* ale rd multiplexed address and data unmultiplexed address t avll t llrl t llax t rldv t avdva t rlrh t rhdz t dxua t rhdx a4-a11 figure 23. external data memory read cycle (non-ale cycle) a0-a3,a12-a19 a0-a3, a12-a19 d0-d7 data in* ale rd multiplexed address and data unmultiplexed address t avdvb 48 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA a4-a11 or a4-a15 * instr in is either d0-d7 or d0-d15, depending on the bus width (8 or 16 bits). figure 24. external data memory write cycle a0 or a1-a3, a12-19 data out* ale wrl or wrh multiplexed address and data unmultiplexed address t avll t qvwx t llwl t llax t avwl t wlwh t uawh t whqx (the dashed line shows the strobe without wait.) figure 25. wait signal timing xtal1 ale address bus wait bus strobe (wrl,wrh, rd,or psen) t crar t wth t wtl 49 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA 0.2vdd+0.9 0.2vdd-0.1 vdd-0.5 0.45v note: ac inputs during testing are driven at vdd-0.5 for a logic "1" and 0.45v for logic "0". timing measurements are made at the 50% point of transitions. timing reference points vload+0.1v vload-0.1v vol+0.1v voh-0.1v vload note: for timing purposes, a port is no longer floating when a 100mv change from load voltage occurs, and begins to float when a 100mv change from the loaded voh/vol level occurs. ioh/iol > 20ma figure 26. external clock drive t chcx t c t chcl 0.7vdd 0.2vdd-0.1 0.45v vdd-0.5 t clcx t chch 50 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA rst (nc) clock signal xtal2 xtal1 vss vdd vdd figure 29. idd test condition, active mode all other pins are disconnected ea rst (nc) clock signal xtal2 xtal1 vss vdd vdd figure 30. idd test condition, idle mode all other pins are disconnected ea vdd frequency (mhz) current(ma) max.idd (active) max.idd (idle) 30 25 20 15 10 5 20 13 40 60 80 100 120 0 figure 31. idd vs. frequency valid only within frequency specification of the device under test. 51 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA rst (nc) xtal2 xtal1 vss vdd vdd figure 33. idd test condition, power down mode all other pins are disconnected. vdd=2v to 5.5v ea vdd figure 32. clock signal waveform for idd tests in active and idle modes t clch= t chcl=5ns t chcx t cl t chcl 0.7vdd 0.2vdd-0.1 0.45v vdd-0.5 t clcx t clch 52 p/n:pm0625 rev. 1.1, may 05, 1999 MX10EXA package information 44-pin plastic leaded chip carrier(plcc) item millimeters inches a 17.53 .12 .690 .005 b 16.59 .12 .653 .005 c 16.59 .12 .653 .005 d 17.53 .12 .690 .005 e 1.95 .077 f 4.70 max. .185 max g 2.55 .25 .100 .010 h .51 min. .020 min. i 1.27 [typ.] .050 [typ.] j .71 .10 .028 .004 k .46 .10 .018 .004 l 15.50 .51 .610 .020 m .63 r .025 r n .25 [typ.] .010 [typ.] f g h i k j m n e l cd b a 640 44 1 13 7 17 18 28 23 33 39 29 n m k j l i h g f e c d p o b a 11 12 1 22 23 33 34 44 item millimeters inches a 17.53 .12 .690 .005 b 16.59 .12 .653 .005 c 16.59 .12 .653 .005 d 17.53 .12 .690 .005 e 1.95 .077 f 4.70 max. .185 max g 2.55 .25 .100 .010 h .51 min. .020 min. i 1.27 [typ.] .050 [typ.] j .71 .10 .028 .004 k .46 .10 .018 .004 l 15.50 .51 .610 .020 m .63 r .025 r n .25 [typ.] .010 [typ.] 44-pin plastic low profile quad flat (lqfp) m acronix i nternational c o., l td. headquarters: tel:+886-3-578-6688 fax:+886-3-563-2888 europe office: tel:+32-2-456-8020 fax:+32-2-456-8021 japan office: tel:+81-44-246-9100 fax:+81-44-246-9105 singapore office: tel:+65-348-8385 fax:+65-348-8096 taipei office: tel:+886-2-2509-3300 fax:+886-2-2509-2200 m acronix a merica, i nc. tel:+1-408-453-8088 fax:+1-408-453-8488 chicago office: tel:+1-847-963-1900 fax:+1-847-963-1909 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice. 9 MX10EXA |
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